\doxysection{FMC\+\_\+\+Bank3\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_m_c___bank3___type_def}{}\label{struct_f_m_c___bank3___type_def}\index{FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}}


Flexible Memory Controller Bank3.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank3___type_def_ad7e74bf59532cbe667231e321bdf0de2}{PCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank3___type_def_a43af4c901144f747741adbf1a479586a}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank3___type_def_af34d82c290385286c11648a983ab3e71}{PMEM}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank3___type_def_a4cca3d0ef62651cc93d4070278bb5376}{PATT}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank3___type_def_a778e98be0b9c57bec95e25b2be2ecd72}{RESERVED}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank3___type_def_ab6c1398fb7158f021ab78a4231c67054}{ECCR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Flexible Memory Controller Bank3. 

\label{doc-variable-members}
\Hypertarget{struct_f_m_c___bank3___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_m_c___bank3___type_def_ab6c1398fb7158f021ab78a4231c67054}\index{FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}!ECCR@{ECCR}}
\index{ECCR@{ECCR}!FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ECCR}{ECCR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank3___type_def_ab6c1398fb7158f021ab78a4231c67054} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank3\+\_\+\+Type\+Def\+::\+ECCR}

NAND Flash ECC result registers 3, Address offset\+: 0x94 \Hypertarget{struct_f_m_c___bank3___type_def_a4cca3d0ef62651cc93d4070278bb5376}\index{FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}!PATT@{PATT}}
\index{PATT@{PATT}!FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PATT}{PATT}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank3___type_def_a4cca3d0ef62651cc93d4070278bb5376} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank3\+\_\+\+Type\+Def\+::\+PATT}

NAND Flash Attribute memory space timing register 3, Address offset\+: 0x8C \Hypertarget{struct_f_m_c___bank3___type_def_ad7e74bf59532cbe667231e321bdf0de2}\index{FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}!PCR@{PCR}}
\index{PCR@{PCR}!FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PCR}{PCR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank3___type_def_ad7e74bf59532cbe667231e321bdf0de2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank3\+\_\+\+Type\+Def\+::\+PCR}

NAND Flash control register 3, Address offset\+: 0x80 \Hypertarget{struct_f_m_c___bank3___type_def_af34d82c290385286c11648a983ab3e71}\index{FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}!PMEM@{PMEM}}
\index{PMEM@{PMEM}!FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PMEM}{PMEM}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank3___type_def_af34d82c290385286c11648a983ab3e71} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank3\+\_\+\+Type\+Def\+::\+PMEM}

NAND Flash Common memory space timing register 3, Address offset\+: 0x88 \Hypertarget{struct_f_m_c___bank3___type_def_a778e98be0b9c57bec95e25b2be2ecd72}\index{FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}!RESERVED@{RESERVED}}
\index{RESERVED@{RESERVED}!FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED}{RESERVED}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank3___type_def_a778e98be0b9c57bec95e25b2be2ecd72} 
uint32\+\_\+t FMC\+\_\+\+Bank3\+\_\+\+Type\+Def\+::\+RESERVED}

Reserved, 0x90 \Hypertarget{struct_f_m_c___bank3___type_def_a43af4c901144f747741adbf1a479586a}\index{FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}!SR@{SR}}
\index{SR@{SR}!FMC\_Bank3\_TypeDef@{FMC\_Bank3\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank3___type_def_a43af4c901144f747741adbf1a479586a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank3\+\_\+\+Type\+Def\+::\+SR}

NAND Flash FIFO status and interrupt register 3, Address offset\+: 0x84 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
